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| features total dose capability to 100 krads(si) floating channel designed for bootstrap operation fully operational to +400v tolerant to negative transient voltage dv/dt immune gate drive supply range from 10 to 20v undervoltage lockout for both channels separate logic supply range from 5 to 20v logic and power ground 5v offset cmos schmitt-triggered inputs with pull-down cycle by cycle edge-triggered shutdown logic matched propagation delay for both channels outputs in phase with inputs hermetically sealed lightweight radiation hardened high and low side gate driver product summary v offset 400v max. i o +/- 2a / 2a v out 10 - 20v t on/off (typ.) 120 & 100 ns delay matching(typ.) 5 ns absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. description the ric7113l4 is a high voltage, high speed power mosfet and igbt driver with independent high and low side referenced output channels. proprietary hvic and latch immune cmos technologies enable ruggedized monolithic construction. logic inputs are compatible with standard cmos or lsttl outputs. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use in high frequency applications. the floating channel can be used to drive an n-channel power mosfet or igbt in the high side configuration which operates up to 400 volts. ! ! !" #"$% "$&'( ) * + , - # - ( ) . . !/ . -' 0, 12 3 4 5 , -6 5 ! %7! 2 38#,( 39 5 , -6 5 ! %7! 3#,( 12)4 5 , -6 5 ! %7! #,( , 7! , 6 - - 3 , - , 6 - - 3 12 , , 6 - - # -%3 ! ( 8 4 38#! ( guaranteed by design, not tested 10/29/14 www.irf.com 1 pd-93921e 2 www.irf.com ric7113l4 ,-.- ' 3 3 9 : ,-.- ' 3 3 : .- ' 33 3 8 : ,-5 ,6 8 2 :3 ,- ,6 3; 2 :3 <, ' < !%& ,-) = = -= = recommended operating conditions the input/output logic timing diagram is shown in figure 1. the v s and v ss offset ratings are tested with all supplies biased at 15v differential. > *+ 3 > 22 3 22 '' ! ! "$ !" #"$% "$&'( '' ns dynamic electrical characteristics v bias (v cc , v bs , v dd ) = 15v, and v ss = com unless otherwise specified. the dynamic electrical characteristics are measured using the test circuit shown in figure 3. typical connection pre-irradiation hin up to 500v to loa d v dd v b v s ho lo com hi n lin v ss sd v cc lin v dd sd v ss v cc ric7113l4 www.irf.com 3 !?3@" 83 88 '' : 9 9a '' :3 b 3 '' :3 3 388 '' : !?@" 39 39 '' : 8a 89 '' :3 9 ; '' :3 a8 ;b '' : c % 3 3 : " :* c % 3 3 : " :* " / 2-- : : " d ! 2-- 8 e* : - " d ! 2-- 8 9 : - " d ! 2-- 8 9 : - " !?3@"> 2-- ; : " !?@"> 2-- 3 3 : f -c . c ; b; g ,- f -c $ c ; b g ,- f -c . c ; b9 g ,- f -c $ c ; b g ,- " -2-!. :% : 2-- * .4 < 3e " -2-!. :3% : 2-- .4 < 3e static electrical characteristics v bias (v cc , v bs , v dd ) = 15v, unless otherwise specified. the v in , v th and i in parameters are refer- enced to v ss and are applicable to all three logic input pins: hin, lin and sd. the v o and i o parameters are referenced to com or v s and are applicable to the respective output pins: ho or lo. pre-irradiation guaranteed by design, not tested 4 www.irf.com ric7113l4 radiation characteristics radiation performance international rectifier radiation hardened gate drivers are tested to verify their hardness capability. the hardness assurance program at international rectifier uses a cobalt-60 ( 60 co) source and heavy ion irradiation. every wafer shall be tested per mil-std-883, method 1019, test condition a ?ionizing radiation (total dose) test procedure?. both pre- and post- irradiation performances are tested and specified using the same drive circuitry and test conditions to provide a direct comparison. for static irradiation test conditions refer to figure 7. static electrical characteristics tj = 25c symbol parameter 100k rads (si) units test conditions min max v ih logic ?1? input voltage 3.1 ? vdd = 5v 6.4 ? vdd = 10v 9.5 ? vdd = 15v 12.5 ? vdd = 20v v il logic ?0? input voltage ? 1.6 vdd = 5v ? 3.8 vdd = 10v 6.0 vdd = 15v ? 8.3 vdd = 20v c % ? 1.2 v in =v ih, i o = 0a c % 0.1 v in =v ih, i o = 0a " / 2-- 50 vb =vs = 400v " d ! 2-- 230 vin =0v or vdd " d ! 2-- 340 vin =0v or vdd " d ! 2-- 30 vin =0v or vdd " !?3@"> 2-- 40 vin =vdd " !?@"> 2-- 1.0 vin =0v f -c . c 7.5 9.7 g ,- f -c $ c 7.0 9.4 g ,- f -c . c 7.4 9.9 g ,- f -c $ c 7.0 9.6 g ,- " -2-!. 2.0 vo =0v, vin =vdd 2-- pw < 10 s " -2-!. 2.0 vo =15v, vin =0v 2-- pw < 10 s a v v a v guaranteed by design, not tested ric7113l4 www.irf.com 5 international rectifier radiation hardened gate drivers have been characterized in heavy ion environment for single event effects (see). single event effects characterization data is illustrated below. for static bias test conditions refer to figure 8. single event effect safe operating area ion let energy angle v s (v) mev/(mg/cm 2 )) (mev) (degrees) @v bs = 10v @v bs = 15v @v bs = 17.5v br 37 284 0 400 400 400 i 60 344 0 325 250 200 au 82 346 0 250 200 175 i 85 344 45 400 400 350 au 100 346 35 400 400 350 note: vcc/vdd = 20v, except for let=100, then vcc/vdd = 17.5v single event effect, safe operating area radiation characteristics static bias 0 50 100 150 200 250 300 350 400 450 -10 -15 -17.5 vb (v) vs (v) br, 0 angle i, 0 angle au, 0 angle i, 45 angle au, 35 angle 3 3 3; 6 www.irf.com ric7113l4 figure 1. input/output logic timing diagram figure 2. floating supply voltage transient test circuit figure 3. switching time test circuit figure 4. switching time waveform definition figure 6. delay matching waveform definitions figure 5. shutdown waveform definitions hv = 10 to 400v (0 to 400v) irf820a ric7113 ric7113 hin lin t r t on t f t off ho lo 50% 50% 90% 90% 10% 10% sd t sd ho lo 50% 90% hin li n ho 50% 50% 10% lo 90% mt ho lo mt ric7113l4 www.irf.com 7 ric7113l4 schematic 2 logic 20v 20v 400v 4k 4k 4k 50 2.4k vdd hin lin sd vss vb ho vs vcc lo com ric7113 1 nf 1 nf figure 7. static bias conditions for total ionizing dosetest figure 8. static bias conditions for single event effect test 8 www.irf.com ric7113l4 v b sd lin v dd pulse gen r s q v ss uv detect delay hv level shift v cc pu lse filter uv detect v dd /v cc leve l shift v dd /v cc leve l sh ift lo v s com r s q r s r q hin ho '' ! " # $%& ! " # ' ( !( ! ) # # *$+,- ( . ! " # ' (# / %& ! " # ' / ! ) # # * +,- ( ! " ! # > $ !( ' ! # $+ $ !( ! ) # # $ !( ' ! # # 22 / # + / ! ) # # + / # lead definitions functional block diagram ric7113l4 www.irf.com 9 case outline and dimensions ? mo-036ab package ir world headquarters: 101 n. sepulveda blvd., el segundo, california 90245, usa tel: (310) 252-7105 ir leominster : 205 crawford st., leominster, massachusetts 01453, usa tel: (978) 534-5776 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . data and specifications subject to change without notice. 10/2014 |
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